Mixture encoder and virtual RAM-based polar decoder architecture for high-speed 5G communication systems

This research presents an optimized architecture for Fifth Generation (5G) communication systems that includes a Mixture Encoder to support multiple combinations of Digital Signal Processing (DSP) operations required for 5G baseband processing. This allows flexible encoding with lower computational overhead, in contrast to traditional polar encoders that rely on fixed arithmetic structures and sizable lookup tables. The lookup table complexity is greatly reduced, resulting in lower memory consumption and faster access, and it also maps ranges to compact intervals. A Built-In Self-Test (BIST) module is integrated before the Mixture Encoder to ensure dependable data feeding and fault tolerance. Furthermore, a virtual channel method developed with Virtual RAM technology eliminates explicit channel processing by allowing direct memory access, bypassing redundant channel operations, and allowing conditional decoding termination before execution. This virtualized method enables early-stage error correction while increasing processing speed, reducing switching activity, and optimizing memory usage. At the receiver, a Successive Cancellation (SC) polar decoder is used to achieve low-latency, energy-efficient decoding. Removing unnecessary operations and enabling sequential recursive decoding reduces arithmetic complexity. According to the FPGA synthesis results, the combination of a mixture encoder, virtual memory access, and SC decoding results in lower power consumption, nanosecond-scale delay, improved decoding precision, and scalable hardware utilization, making the proposed architecture ideal for DSP-intensive communication systems and 5G networks.